Programmable logic devices, such as field programmable gate arrays (FPGAs) are digital logic circuits that can be programmed to perform a variety of logical functions. A specific logical function is programmed into a programmable logic device by a user. A user may subsequently overwrite the initial logical function with a new logical function. To that end, FPGAs include an array of programmable logic blocks in data communication with input/output (I/O) circuitry. I/O pads are in data communication with the I/O circuitry to place the same in data communication with external circuitry. The I/O circuitry functions as an interface with the external circuitry to route signals appropriately to different circuits within the FPGA.
One technique to program an FPGA includes a storage device external to the FPGA and in data communication therewith. The storage device typically has sufficient capacity to store information that facilitates configuration of the logic blocks and additional configuration data, such as user-specific configuration data. The precise capacity required for the storage device is dependent, in part, upon the particular FPGA employed. An example of an FPGA includes the families of devices owned and sold by the assignee. Typically, the storage device for the configuration is an industry-standard Flash memory. It has been observed that the time required to configure the FPGA with information from the storage device upon intialization is increased due to the delay presented by I/O circuitry and the speed at which the data is accessed from the storage device.
The speed that data can be synchronously read from an external memory is limited by the time it takes to generate a clock signal, to send the clock signal to the memory, for the memory to transmit the data and for the sender to capture the data. Currently, the limitations on the configuration time for programmable logic devices discourages customers away from FPGAs and towards application specific integrated circuits in certain instances.
Thus, there is a need for improved performance when configuring FPGAs.